The invention relates to an integrated circuit for the processing of digitised signals which are representative of a source image which is defined by image elements which are encoded on M bits and which are arranged in I rows and J columns, the processing of said source image being performed by step-wise fetching local images which are defined by a window N.P consisting of N rows (wherein N&gt;1) and P columns and sliding step-wise past each image element along the I rows of the source image. The invention also relates to an image processing device for covering any such configuration for which no window extends outside the source image.
An invention of this kind is known from U.S. Pat. No. 4,550,437 which discloses an apparatus for the parallel processing of local image data. The object is to conceive a large scale integrated circuit performing convolution type image processing procedures for various purposes (e.g. elimination of noise, detection of contours, . . . ). Difficulties encountered concern the high integration density and the large number of connection pads required for the integrated circuit. The processing consists of defining a local image which is taken from the overall image by means of a window and which comprises m rows of n elements. The described integrated circuit comprises 4 arrays of 4 elements which are processed by 4 memories and 4 processors for the processing of a 4.times.4 window. The bits of an image element are introduced in parallel into the first stage, are processed and subsequently shifted to the next processor and so on until all results are added in order to supply the desired result. However, when the width of the window is very large, the realisation of an integrated circuit where the bits are introduced in parallel quickly becomes impossible to realise because of the number of connections to the environment. Moreover, nothing is indicated as regards the realisation of the delay circuits, notably not as regards their integration.